In recent years DRAM (Dynamic Random Access Memory) and flash memory are widely used as volatile and non-volatile semiconductor memory devices, respectively. With the aim of replacing these memories, there is progress in the development of various types of semiconductor memory device. Among these, variable resistance memory cells are known, in which variable resistance elements are used to store information of logic 0 and logic 1 according to resistance states thereof.
There are two ways of writing to the variable resistance elements: writing by changing a high resistance state to a low resistance state, and writing by changing a low resistance state to a high resistance state. As an example of a write operation, a bipolar switching type of variable resistance memory cell is known, in which the direction of voltage or current applied to a variable resistance element, is reversed, according to a case of writing information of logic 0 and a case of writing information of logic 1.
For example, a bipolar switching type of variable resistance element may be an STT-RAM (Spin Transfer Torque-Random Access Memory) that performs spin injection magnetization reversal writing using a magnetic tunnel junction (MTJ) element, or a Re-RAM (Resistance-Random Access Memory) that uses a metal oxide or the like.
Yahya Lakys, etc. “Self-Enabled “Error-Free” Switching Circuit for Spin Transfer Torque MRAM and Logic,” IEEE TRANSACTIONS ON MAGNETICS, Vol. 48, No. 9, September 2012 (Non-Patent Literature 1) discloses an STT-RAM and an example of a bipolar switching type of write operation in an STT-RAM.
It is to be noted that the disclosure of the abovementioned related technology is incorporated herein by reference thereto.
The following analysis is given by the present inventors.
In general, with regard to one write operation for a certain one memory cell (for example, an operation of changing logic information indicated by one memory cell from logic 0 to logic 1), consideration is given to using either one of (i) one write pulse with a long time of application, or (ii) multiple write pulses of short time of application.
The Non-Patent Literature 1 principally discloses the abovementioned (i) as a “conventional” means, and the above-mentioned (ii) as a “proposed” means, in FIG. 4.
In the write operation (FIG. 4) proposed by the Non-Patent Literature 1, a whole write pulse when writing data to a magnetic tunnel junction element is divided into pulses of short duration, reads the magnetic tunnel junction element state immediately after pulse application, and stops application of the write pulse at a point in time at which the writing is judged to have succeeded.
In a write operation with regard to a general STT-RAM as described above, use of the abovementioned (i) one write pulse with a long time of application, is considered to be mainstream, but the technology proposed by this Non-Patent Literature 1 is different therefrom.
In the Non-Patent Literature 1, with regard to a write operation of either of the abovementioned (i) and (ii), there is no mention concerning how to obtain the time for which a write current is applied, or the duration of a write pulse. That is, Non-Patent Literature 1 has no mention at all concerning how to determine the pulse duration necessary for writing to a memory cell (in other words, optimum time for application of a write current or voltage) as an optimum value, or how to obtain the optimum, value thereof.
In addition, in a write operation in the abovementioned (ii) proposal of the Non-Patent Literature 1, application of a write pulse and comparison reading are alternately repeated. Application of a write pulse is ended when a comparison reading result (self-enable signal) is generated. The comparison reading result indicates that the resistance value of a memory cell has changed, that is, when magnetization direction of an MTJ element changes from a parallel state to an antiparallel state or from an anti parallel state to a parallel state. As a result, it is understood that there is no problem with regard to operation if the duration of one write pulse, as proposed by the Non-Patent Literature 1, even with somewhat rough adjustment, is sufficiently short.
It is to be noted that the following problem may be pointed out. In the technology disclosed by the Non-Patent Literature 1, there is a problem in that, since the state of the magnetic tunnel junction element is read each time a short pulse is applied, with regard to an overall data writing process, the write time increases. Furthermore, when the state of the magnetic tunnel junction element is read, in a case where the direction of current applied to the magnetic tunnel junction element is different from the direction of write current, read operations disturb write operations, and write time is further increased. As described above, in the technology disclosed by the Non-Patent Literature 1, the time for writing data to the magnetic tunnel junction element may increase.